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1 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b 64m-bit [8m x 8/4m x 16] single voltage 3v only flash memory features general features ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program opera- tions ? 8,388,608 x 8 / 4,194,304 x 16 switchable ? sector structure - 8kb (4kw) x 8 and 64kb(32kw) x 127 ? sector protection/chip unprotect - provides sector group protect function to prevent program or erase operation in the protected sector group - provides chip unprotect function to allow code changes - provides temporary sector group unprotect function for code changes in previously protected sector groups ? secured silicon sector - provides a 128-word area for code or data that can be permanently protected. - once this sector is protected, it is prohibited to pro- gram or erase within the sector again. ? latch-up protected to 250ma from -1v to vcc + 1v ? low vcc write inhibit is equal to or less than 1.5v ? compatible with jedec standard - pin-out and software compatible to single power sup- ply flash performance ? high performance - fast access time: 90/120ns - fast program time: 11us/word, 45s/chip (typical) - fast erase time: 0.9s/sector, 45s/chip (typical) ? low power consumption - low active read current: 10ma (typical) at 5mhz - low standby current: 0.2ua (typ.) ? minimum 100,000 erase/program cycle ? 20-year data retention software features ? support common flash interface (cfi) - flash device parameters stored on the device and provide the host system to access. ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data polling & toggle bits provide detection of pro- gram and erase operation completion hardware features ? ready/busy (ry/by) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset) input - provides a hardware method to reset the internal state machine to read mode ? wp pin - write protect (wp) function allows protection of two outermost boot sectors, regardless of sector protect status package ? 48-pin tsop ? 63-ball csp ? 64-ball easy bga general description the mx29lv640t/b is a 64-mega bit flash memory or- ganized as 8m bytes of 8 bits or 4m bytes of 16 bits. mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx29lv640t/b is packaged in 48-pin tsop, 63- ball csp and 64-ball easy bga. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx29lv640t/b offers access time as fast as 90ns, allowing operation of high-speed microproces- sors without wait states. to eliminate bus contention, the mx29lv640t/b has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the
2 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b mx29lv640t/b uses a command register to manage this functionality. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29lv640t/b uses a 2.7v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamperes on address and data pin from -1v to vcc + 1v. automatic programming the mx29lv640t/b is byte/word programmable using the automatic programming algorithm. the automatic programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. the typical chip programming time at room temperature of the mx29lv640t/b is less than 50 seconds. automatic programming algorithm mxic's automatic programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and a0h) and a program command (pro- gram data and address). the device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. a status bit similar to data polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic chip erase the entire chip is bulk erased using 50 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 115 seconds. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the mx29lv640t/b is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically pro- grams the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are con- trolled internally within the device. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx29lv640t/b elec- trically erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
3 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b pin configuration 48 tsop 63 ball csp (top view, ball down) a13 a9 we ry/by a7 a3 a * ball are shorted together via the substrate but not connected to the die. 8 7 6 5 4 3 2 1 bcdef ghjk lm a12 nc nc a8 reset wp a17 a4 a14 a10 a21 a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 q7 q5 q2 q0 a0 byte q14 q12 q10 q8 ce q15/ a-1 q13 vcc q11 q9 oe gnd q6 q4 q3 q1 gnd nc* nc* nc* nc* 12.0 mm 11.0 mm nc* nc* nc nc nc* nc* nc* nc* nc* a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we reset a21 wp ry/by a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe gnd ce a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx29lv640t/b
4 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b symbol pin name a0~a21 address input q0~q14 data inputs/outputs q15/a-1 q15(word mode)/lsb addr(byte mode) ce chip enable input we write enable input oe output enable input reset hardware reset pin, active low wp hardware write protect ry/by read/busy output vcc +3.0v single power supply gnd device ground nc pin not connected internally pin description logic symbol 64 ball easy bga (top view, ball down) a8 13mm 10 mm b8 c8 d8 nc e8 gnd f8 nc nc nc nc nc nc g8 h8 a7 a13 b7 a12 c7 a14 d7 a15 e7 a16 f7 byte g7 q15 h7 gnd a6 a9 b6 a8 c6 a10 d6 a11 e6 q7 f6 q14 g6 q13 h6 q6 a5 we b5 reset c5 a21 d5 a19 e5 q5 f5 q12 g5 vcc h5 q4 a4 ry/by b4 wp c4 a18 d4 a20 e4 q2 f4 q10 g4 q11 h4 q3 a3 a7 b3 a17 c3 a6 d3 a5 e3 q0 f3 q8 g3 q9 h3 q1 a2 a3 b2 a4 c2 a2 d2 a1 e2 a0 f2 ce g2 oe h2 gnd a1 b1 c1 d1 e1 f1 nc g1 nc h1 nc nc nc nc nc nc 16 or 8 q0-q15 (a-1) ry/by a0-a21 wp ce oe we reset 22
5 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx29lv640t/b flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-a21 ce oe we wp byte reset
6 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 1 sa0 0000000xxx 64/32 000000h-00ffffh 000000h-07fffh 1 sa1 0000001xxx 64/32 010000h-01ffffh 008000h-0ffffh 1 sa2 0000010xxx 64/32 020000h-02ffffh 010000h-17fffh 1 sa3 0000011xxx 64/32 030000h-03ffffh 018000h-01ffffh 2 sa4 0000100xxx 64/32 040000h-04ffffh 020000h-027fffh 2 sa5 0000101xxx 64/32 050000h-05ffffh 028000h-02ffffh 2 sa6 0000110xxx 64/32 060000h-06ffffh 030000h-037fffh 2 sa7 0000111xxx 64/32 070000h-07ffffh 038000h-03ffffh 3 sa8 0001000xxx 64/32 080000h-08ffffh 040000h-047fffh 3 sa9 0001001xxx 64/32 090000h-09ffffh 048000h-04ffffh 3 sa10 0001010xxx 64/32 0a0000h-0affffh 050000h-057fffh 3 sa11 0001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh 4 sa12 0001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh 4 sa13 0001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh 4 sa14 0001110xxx 64/32 0e0000h-0effffh 070000h-077fffh 4 sa15 0001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh 5 sa16 0010000xxx 64/32 100000h-10ffffh 080000h-087fffh 5 sa17 0010001xxx 64/32 110000h-11ffffh 088000h-08ffffh 5 sa18 0010010xxx 64/32 120000h-12ffffh 090000h-097fffh 5 sa19 0010011xxx 64/32 130000h-13ffffh 098000h-09ffffh 6 sa20 0010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh 6 sa21 0010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh 6 sa22 0010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh 6 sa23 0010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh 7 sa24 0011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh 7 sa25 0011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh 7 sa26 0011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh 7 sa27 0011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh 8 sa28 0011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh 8 sa29 0011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh 8 sa30 0011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh 8 sa31 0011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh 9 sa32 0100000xxx 64/32 200000h-20ffffh 100000h-107fffh 9 sa33 0100001xxx 64/32 210000h-21ffffh 108000h-10ffffh 9 sa34 0100010xxx 64/32 220000h-22ffffh 110000h-117fffh 9 sa35 0100011xxx 64/32 230000h-23ffffh 118000h-11ffffh 10 sa36 0100100xxx 64/32 240000h-24ffffh 120000h-127fffh 10 sa37 0100101xxx 64/32 250000h-25ffffh 128000h-12ffffh 10 sa38 0100110xxx 64/32 260000h-26ffffh 130000h-137fffh 10 sa39 0100111xxx 64/32 270000h-27ffffh 138000h-13ffffh mx29lv640t sector group architecture
7 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 11 sa40 0101000xxx 64/32 280000h-28ffffh 140000h-147fffh 11 sa41 0101001xxx 64/32 290000h-29ffffh 148000h-14ffffh 11 sa42 0101010xxx 64/32 2a0000h-2affffh 150000h-157fffh 11 sa43 0101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh 12 sa44 0101100xxx 64/32 2c0000h-2cffffh 160000h-147fffh 12 sa45 0101101xxx 64/32 2d0000h-2dffffh 168000h-14ffffh 12 sa46 0101110xxx 64/32 2e0000h-2effffh 170000h-177fffh 12 sa47 0101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh 13 sa48 0110000xxx 64/32 300000h-30ffffh 180000h-187fffh 13 sa49 0110001xxx 64/32 310000h-31ffffh 188000h-18ffffh 13 sa50 0110010xxx 64/32 320000h-32ffffh 190000h-197fffh 13 sa51 0110011xxx 64/32 330000h-33ffffh 198000h-19ffffh 14 sa52 0110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh 14 sa53 0110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh 14 sa54 0110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh 14 sa55 0110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh 15 sa56 0111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh 15 sa57 0111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh 15 sa58 0111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh 15 sa59 0111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh 16 sa60 0111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh 16 sa61 0111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh 16 sa62 0111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh 16 sa63 0111111xxx 64/32 3f0000h-3fffffh 1f8000h-1fffffh 17 sa64 1000000xxx 64/32 400000h-40ffffh 200000h-207fffh 17 sa65 1000001xxx 64/32 410000h-41ffffh 208000h-20ffffh 17 sa66 1000010xxx 64/32 420000h-42ffffh 210000h-217fffh 17 sa67 1000011xxx 64/32 430000h-43ffffh 218000h-21ffffh 18 sa68 1000100xxx 64/32 440000h-44ffffh 220000h-227fffh 18 sa69 1000101xxx 64/32 450000h-45ffffh 228000h-22ffffh 18 sa70 1000110xxx 64/32 460000h-46ffffh 230000h-237fffh 18 sa71 1000111xxx 64/32 470000h-47ffffh 238000h-23ffffh 19 sa72 1001000xxx 64/32 480000h-48ffffh 240000h-247fffh 19 sa73 1001001xxx 64/32 490000h-49ffffh 248000h-24ffffh 19 sa74 1001010xxx 64/32 4a0000h-4affffh 250000h-257fffh 19 sa75 1001011xxx 64/32 4b0000h-4bffffh 258000h-25ffffh 20 sa76 1001100xxx 64/32 4c0000h-4cffffh 260000h-247fffh 20 sa77 1001101xxx 64/32 4d0000h-4dffffh 268000h-24ffffh 20 sa78 1001110xxx 64/32 4e0000h-4effffh 270000h-277fffh 20 sa79 1001111xxx 64/32 4f0000h-4fffffh 278000h-27ffffh
8 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 21 sa80 1010000xxx 64/32 500000h-50ffffh 280000h-287fffh 21 sa81 1010001xxx 64/32 510000h-51ffffh 288000h-28ffffh 21 sa82 1010010xxx 64/32 520000h-52ffffh 290000h-297fffh 21 sa83 1010011xxx 64/32 530000h-53ffffh 298000h-29ffffh 22 sa84 1010100xxx 64/32 540000h-54ffffh 2a0000h-2a7fffh 22 sa85 1010101xxx 64/32 550000h-55ffffh 2a8000h-2affffh 22 sa86 1010110xxx 64/32 560000h-56ffffh 2b0000h-2b7fffh 22 sa87 1010111xxx 64/32 570000h-57ffffh 2b8000h-2bffffh 23 sa88 1011000xxx 64/32 580000h-58ffffh 2c0000h-2c7fffh 23 sa89 1011001xxx 64/32 590000h-59ffffh 2c8000h-2cffffh 23 sa90 1011010xxx 64/32 5a0000h-5affffh 2d0000h-2d7fffh 23 sa91 1011011xxx 64/32 5b0000h-5bffffh 2d8000h-2dffffh 24 sa92 1011100xxx 64/32 5c0000h-5cffffh 2e0000h-2e7fffh 24 sa93 1011101xxx 64/32 5d0000h-5dffffh 2e8000h-2effffh 24 sa94 1011110xxx 64/32 5e0000h-5effffh 2f0000h-2f7fffh 24 sa95 1011111xxx 64/32 5f0000h-5fffffh 2f8000h-2fffffh 25 sa96 1100000xxx 64/32 600000h-60ffffh 300000h-307fffh 25 sa97 1100001xxx 64/32 610000h-61ffffh 308000h-30ffffh 25 sa98 1100010xxx 64/32 620000h-62ffffh 310000h-317fffh 25 sa99 1100011xxx 64/32 630000h-63ffffh 318000h-31ffffh 26 sa100 1100100xxx 64/32 640000h-64ffffh 320000h-327fffh 26 sa101 1100101xxx 64/32 650000h-65ffffh 328000h-32ffffh 26 sa102 1100110xxx 64/32 660000h-66ffffh 330000h-337fffh 26 sa103 1100111xxx 64/32 670000h-67ffffh 338000h-33ffffh 27 sa104 1101000xxx 64/32 680000h-68ffffh 340000h-347fffh 27 sa105 1101001xxx 64/32 690000h-69ffffh 348000h-34ffffh 27 sa106 1101010xxx 64/32 6a0000h-6affffh 350000h-357fffh 27 sa107 1101011xxx 64/32 6b0000h-6bffffh 358000h-35ffffh 28 sa108 1101100xxx 64/32 6c0000h-6cffffh 360000h-347fffh 28 sa109 1101101xxx 64/32 6d0000h-6dffffh 368000h-34ffffh 28 sa110 1101110xxx 64/32 6e0000h-6effffh 370000h-377fffh 28 sa111 1101111xxx 64/32 6f0000h-6fffffh 378000h-37ffffh 29 sa112 1110000xxx 64/32 700000h-70ffffh 380000h-387fffh 29 sa113 1110001xxx 64/32 710000h-71ffffh 388000h-38ffffh 29 sa114 1110010xxx 64/32 720000h-72ffffh 390000h-397fffh 29 sa115 1110011xxx 64/32 730000h-73ffffh 398000h-39ffffh 30 sa116 1110100xxx 64/32 740000h-74ffffh 3a0000h-3a7fffh 30 sa117 1110101xxx 64/32 750000h-75ffffh 3a8000h-3affffh 30 sa118 1110110xxx 64/32 760000h-76ffffh 3b0000h-3b7fffh 30 sa119 1110111xxx 64/32 770000h-77ffffh 3b8000h-3bffffh
9 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b top boot security sector addresses sector address sector size (x8) (x16) a21~a12 (bytes/words) address range address range 1111111111 256/128 7fff00h-7fffffh 3fff70h-3fffffh note:the address range is a21:a-1 in byte mode (byte=vil) or a20:a0 in word mode (byte=vih) sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 31 sa120 1111000xxx 64/32 780000h-78ffffh 3c0000h-3c7fffh 31 sa121 1111001xxx 64/32 790000h-79ffffh 3c8000h-3cffffh 31 sa122 1111010xxx 64/32 7a0000h-7affffh 3d0000h-3d7fffh 31 sa123 1111011xxx 64/32 7b0000h-7bffffh 3d8000h-3dffffh 32 sa124 1111100xxx 64/32 7c0000h-7cffffh 3e0000h-3e7fffh 32 sa125 1111101xxx 64/32 7d0000h-7dffffh 3e8000h-3effffh 32 sa126 1111110xxx 64/32 7e0000h-7effffh 3f0000h-3f7fffh 33 sa127 1111111000 8/4 7f0000h-7f1fffh 3f8000h-3fffffh 34 sa128 1111111001 8/4 7f2000h-7f3fffh 3f9000h-3f9fffh 35 sa129 1111111010 8/4 7f4000h-7f5fffh 3f a000h-3fafffh 36 sa130 1111111011 8/4 7f6000h-7f7fffh 3fb000h-3fbfffh 37 sa131 1111111100 8/4 7f8000h-7f9fffh 3fc000h-3fcfffh 38 sa132 1111111101 8/4 7f a000h-7fbfffh 3fd000h-3fdfffh 39 sa133 1111111110 8/4 7fc000h-7fdfffh 3fe000h-3fefffh 40 sa134 1111111111 8/4 7fe000h-7fffffh 3ff000h-3fffffh
10 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 1 sa0 0000000000 8/4 000000h-001fffh 000000h-000fffh 2 sa1 0000000001 8/4 002000h-003fffh 001000h-001fffh 3 sa2 0000000010 8/4 004000h-005fffh 002000h-002fffh 4 sa3 0000000011 8/4 006000h-007fffh 003000h-003fffh 5 sa4 0000000100 8/4 008000h-009fffh 004000h-004fffh 6 sa5 0000000101 8/4 00a000h-00bfffh 005000h-005fffh 7 sa6 0000000110 8/4 00c000h-00dfffh 006000h-006fffh 8 sa7 0000000111 8/4 00e000h-00ffffh 007000h-007fffh 9 sa8 0000001xxx 64/32 010000h-01ffffh 008000h-00ffffh 9 sa9 0000010xxx 64/32 020000h-02ffffh 010000h-017fffh 9 sa10 0000011xxx 64/32 030000h-03ffffh 018000h-01ffffh 10 sa11 0000100xxx 64/32 040000h-04ffffh 020000h-027fffh 10 sa12 0000101xxx 64/32 050000h-05ffffh 028000h-02ffffh 10 sa13 0000110xxx 64/32 060000h-06ffffh 030000h-037fffh 10 sa14 0000111xxx 64/32 070000h-07ffffh 038000h-03ffffh 11 sa15 0001000xxx 64/32 080000h-08ffffh 040000h-047fffh 11 sa16 0001001xxx 64/32 090000h-09ffffh 048000h-04ffffh 11 sa17 0001010xxx 64/32 0a0000h-0affffh 050000h-057fffh 11 sa18 0001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh 12 sa19 0001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh 12 sa20 0001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh 12 sa21 0001110xxx 64/32 0e0000h-0effffh 070000h-077fffh 12 sa22 0001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh 13 sa23 0010000xxx 64/32 100000h-10ffffh 080000h-087fffh 13 sa24 0010001xxx 64/32 110000h-11ffffh 088000h-08ffffh 13 sa25 0010010xxx 64/32 120000h-12ffffh 090000h-097fffh 13 sa26 0010011xxx 64/32 130000h-13ffffh 098000h-09ffffh 14 sa27 0010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh 14 sa28 0010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh 14 sa29 0010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh 14 sa30 0010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh 15 sa31 0011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh 15 sa32 0011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh 15 sa33 0011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh 15 sa34 0011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh 16 sa35 0011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh 16 sa36 0011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh 16 sa37 0011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh 16 sa38 0011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh MX29LV640B sector group architecture
11 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 17 sa39 0100000xxx 64/32 200000h-20ffffh 100000h-107fffh 17 sa40 0100001xxx 64/32 210000h-21ffffh 108000h-10ffffh 17 sa41 0100010xxx 64/32 220000h-22ffffh 110000h-117fffh 17 sa42 0100011xxx 64/32 230000h-23ffffh 118000h-11ffffh 18 sa43 0100100xxx 64/32 240000h-24ffffh 120000h-127fffh 18 sa44 0100101xxx 64/32 250000h-25ffffh 128000h-12ffffh 18 sa45 0100110xxx 64/32 260000h-26ffffh 130000h-137fffh 18 sa46 0100111xxx 64/32 270000h-27ffffh 138000h-13ffffh 19 sa47 0101000xxx 64/32 280000h-28ffffh 140000h-147fffh 19 sa48 0101001xxx 64/32 290000h-29ffffh 148000h-14ffffh 19 sa49 0101010xxx 64/32 2a0000h-2affffh 150000h-157fffh 19 sa50 0101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh 20 sa51 0101100xxx 64/32 2c0000h-2cffffh 160000h-167fffh 20 sa52 0101101xxx 64/32 2d0000h-2dffffh 168000h-16ffffh 20 sa53 0101110xxx 64/32 2e0000h-2effffh 170000h-177fffh 20 sa54 0101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh 21 sa55 0110000xxx 64/32 300000h-30ffffh 180000h-187fffh 21 sa56 0110001xxx 64/32 310000h-31ffffh 188000h-18ffffh 21 sa57 0110010xxx 64/32 320000h-32ffffh 190000h-197fffh 21 sa58 0110011xxx 64/32 330000h-33ffffh 198000h-19ffffh 22 sa59 0110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh 22 sa60 0110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh 22 sa61 0110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh 22 sa62 0110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh 23 sa63 0111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh 23 sa64 0111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh 23 sa65 0111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh 23 sa66 0111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh 24 sa67 0111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh 24 sa68 0111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh 24 sa69 0111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh 24 sa70 0111111xxx 64/32 3f0000h-3fffffh 1f8000h-1fffffh 25 sa71 1000000xxx 64/32 400000h-40ffffh 200000h-207fffh 25 sa72 1000001xxx 64/32 410000h-41ffffh 208000h-20ffffh 25 sa73 1000010xxx 64/32 420000h-42ffffh 210000h-217fffh 25 sa74 1000011xxx 64/32 430000h-43ffffh 218000h-21ffffh 26 sa75 1000100xxx 64/32 440000h-44ffffh 220000h-227fffh 26 sa76 1000101xxx 64/32 450000h-45ffffh 228000h-22ffffh 26 sa77 1000110xxx 64/32 460000h-46ffffh 230000h-237fffh 26 sa78 1000111xxx 64/32 470000h-47ffffh 238000h-23ffffh
12 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 27 sa79 1001000xxx 64/32 480000h-48ffffh 240000h-247fffh 27 sa80 1001001xxx 64/32 490000h-49ffffh 248000h-24ffffh 27 sa81 1001010xxx 64/32 4a0000h-4affffh 250000h-257fffh 27 sa82 1001011xxx 64/32 4b0000h-4bffffh 258000h-25ffffh 28 sa83 1001100xxx 64/32 4c0000h-4cffffh 260000h-267fffh 28 sa84 1001101xxx 64/32 4d0000h-4dffffh 268000h-26ffffh 28 sa85 1001110xxx 64/32 4e0000h-4effffh 270000h-277fffh 28 sa86 1001111xxx 64/32 4f0000h-4fffffh 278000h-27ffffh 29 sa87 1010000xxx 64/32 500000h-50ffffh 280000h-287fffh 29 sa88 1010001xxx 64/32 510000h-51ffffh 288000h-28ffffh 29 sa89 1010010xxx 64/32 520000h-52ffffh 290000h-297fffh 29 sa90 1010011xxx 64/32 530000h-53ffffh 298000h-29ffffh 30 sa91 1010100xxx 64/32 540000h-54ffffh 2a0000h-2a7fffh 30 sa92 1010101xxx 64/32 550000h-55ffffh 2a8000h-2affffh 30 sa93 1010110xxx 64/32 560000h-56ffffh 2b0000h-2b7fffh 30 sa94 1010111xxx 64/32 570000h-57ffffh 2b8000h-2bffffh 31 sa95 1011000xxx 64/32 580000h-58ffffh 2c0000h-2c7fffh 31 sa96 1011001xxx 64/32 590000h-59ffffh 2c8000h-2cffffh 31 sa97 1011010xxx 64/32 5a0000h-5affffh 2d0000h-2d7fffh 31 sa98 1011011xxx 64/32 5b0000h-5bffffh 2d8000h-2dffffh 32 sa99 1011100xxx 64/32 5c0000h-5cffffh 2e0000h-2e7fffh 32 sa100 1011101xxx 64/32 5d0000h-5dffffh 2e8000h-2effffh 32 sa101 1011110xxx 64/32 5e0000h-5effffh 2f0000h-2f7fffh 32 sa102 1011111xxx 64/32 5f0000h-5fffffh 2f8000h-2fffffh 33 sa103 1100000xxx 64/32 600000h-60ffffh 300000h-307fffh 33 sa104 1100001xxx 64/32 610000h-61ffffh 308000h-30ffffh 33 sa105 1100010xxx 64/32 620000h-62ffffh 310000h-317fffh 33 sa106 1100011xxx 64/32 630000h-63ffffh 318000h-31ffffh 34 sa107 1100100xxx 64/32 640000h-64ffffh 320000h-327fffh 34 sa108 1100101xxx 64/32 650000h-65ffffh 328000h-32ffffh 34 sa109 1100110xxx 64/32 660000h-66ffffh 330000h-337fffh 34 sa110 1100111xxx 64/32 670000h-67ffffh 338000h-33ffffh 35 sa111 1101000xxx 64/32 680000h-68ffffh 340000h-347fffh 35 sa112 1101001xxx 64/32 690000h-69ffffh 348000h-34ffffh 35 sa113 1101010xxx 64/32 6a0000h-6affffh 350000h-357fffh 35 sa114 1101011xxx 64/32 6b0000h-6bffffh 358000h-35ffffh 36 sa115 1101100xxx 64/32 6c0000h-6cffffh 360000h-367fffh 36 sa116 1101101xxx 64/32 6d0000h-6dffffh 368000h-36ffffh 36 sa117 1101110xxx 64/32 6e0000h-6effffh 370000h-377fffh 36 sa118 1101111xxx 64/32 6f0000h-6fffffh 378000h-37ffffh
13 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b bottom boot security sector addresses sector address sector size (x8) (x16) a21~a12 (bytes/words) address range address range 0000000000 256/128 000000h-0000ffh 000000-00007fh note:the address range is a20:a-1 in byte mode (byte=vil) or a20:a0 in word mode (byte=vih) sector sector sector address sector size (x8) (x16) group a21-a12 (kbytes/kwords) address range address range 37 sa119 1110000xxx 64/32 700000h-70ffffh 380000h-387fffh 37 sa120 1110001xxx 64/32 710000h-71ffffh 388000h-38ffffh 37 sa121 1110010xxx 64/32 720000h-72ffffh 390000h-397fffh 37 sa122 1110011xxx 64/32 730000h-73ffffh 398000h-39ffffh 38 sa123 1110100xxx 64/32 740000h-74ffffh 3a0000h-3a7fffh 38 sa124 1110101xxx 64/32 750000h-75ffffh 3a8000h-3affffh 38 sa125 1110110xxx 64/32 760000h-76ffffh 3b0000h-3b7fffh 38 sa126 1110111xxx 64/32 770000h-77ffffh 3b8000h-3bffffh 39 sa127 1111000xxx 64/32 780000h-78ffffh 3c0000h-3c7fffh 39 sa128 1111001xxx 64/32 790000h-79ffffh 3c8000h-3cffffh 39 sa129 1111010xxx 64/32 7a0000h-7affffh 3d0000h-3d7fffh 39 sa130 1111011xxx 64/32 7b0000h-7bffffh 3d8000h-3dffffh 40 sa131 1111100xxx 64/32 7c0000h-7cffffh 3e0000h-3e7fffh 40 sa132 1111101xxx 64/32 7d0000h-7dffffh 3e8000h-3effffh 40 sa133 1111110xxx 64/32 7e0000h-7effffh 3f0000h-3f7fffh 40 sa134 1111111xxx 64/32 7f0000h-7fffffh 3f8000h-3fffffh
14 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b operation ce oe we reset wp address q15~q0 read l l h h l/h a in d out write (program/erase) l h l h (note 2) a in d in standby vcc 0.3v x x vcc 0.3v h x high-z output disable l h h h l/h x high-z reset x x x l l/h x high-z sector group protect l h l v id l/h sector addresses, d in , d out (note 2) a6=l, a1=h, a0=l chip unprotect l h l v id (note 2) sector addresses, d in , d out (note 2) a6=h, a1=h, a0=l temporary sector group x x x v id (note 2) a in d in unprotect legend: l=logic low=v il , h=logic high=v ih , v id =12.0 0.5v, x=don't care, a in =address in, d in =data in, d out =data out notes: 1. the sector group protect and chip unprotect functions may also be implemented via programming equipment. see the "sector group protection and chip unprotect" section. 2. if wp=vil, the two outermost boot sectors remain protected. if wp=vih, the two outermost boot sector protec- tion depends on whether they were last protected or unprotect using the method described in "sector/ sector block protection and unprotect". 3. d in or d out as required by command sequence, data polling or sector protect algorithm (see figure 2). table 1 bus operation (1)
15 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b operation ce oe we a0 a1 a5 a6 a8 a9 a14 a15 q0~q15 to to to to a2 a7 a10 a21 manufactures code l l h l l x x x v id x x xxc2h read device code l l h h l x x x v id x x 22c9h (word) silicon (top boot block) xxc9h (byte) id device code l l h h l x x x v id x x 22cbh (word) (bottom boot block) xxcbh (byte) sector protect verify l l h x h x x x v id x sa code(1) secured silicon sector xx88h indicator bit (q7) l l h h h x l x v id x x (factory locked) xx08h (non-factory locked) autoselect codes (high voltage method) notes: 1.code=xx00h means unprotected, or code=xx01h means protected, sa=sector address, x=don't care.
16 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b requirements for reading array data to read array data from the outputs, the system must drive the ce and oe pins to vil. ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device or erase sectors of memory , the system must drive we and ce to vil, and oe to vih. an erase operation can erase one sector, multiple sectors , or the entire device. table indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. the "writing specific address and data commands or sequences into the command register initiates device operations. table 1 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the automatic select command sequence, the device enters the automatic select mode. the system can then read automatic select codes from the internal register (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the automatic select mode and automatic select command sequence section for more information. icc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. standby mode mx29lv640t/b can be set into standby mode with two different approaches. one is using both ce and reset pins and the other one is using reset pin only. when using both pins of ce and reset, a cmos standby mode is achieved with both pins held at vcc 0.3v. under this condition, the current consumed is less than 0.2ua (typ.). if both of the ce and reset are held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby current will be larger. during auto algorithm operation, vcc ac- tive current (icc2) is required even ce = "h" until the operation is completed. the device can be read with stan- dard access time (tce) from either of these standby modes. when using only reset, a cmos standby mode is achieved with reset input held at vss 0.3v, under this condition the current is consumed less than 1ua (typ.). once the reset pin is taken high, the device is back to active without recovery delay. in the standby mode the outputs are in the high imped- ance state, independent of the oe input. mx29lv640t/b is capable to provide the automatic standby mode to restrain power consumption during read- out of data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to active this mode, mx29lv640t/b automatically switch themselves to low power mode when mx29lv640t/b addresses remain stable during access time of tacc+30ns. it is not necessary to control ce, we, and oe on the mode. under the mode, the current consumed is typically 0.2ua (cmos level). automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when address remain stable for tacc+30ns. the automatic sleep mode is independent of the ce, we, and oe control signals. standard address access tim- ings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. icc4 in the dc characteristics table represents the automatic sleep mode current specifica- tion.
17 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b output disable with the oe input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. reset operation the reset pin provides a hardware method of resetting the device to reading array data. when the reset pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity current is reduced for the duration of the reset pulse. when reset is held at vss 0.3v, the device draws cmos standby current (icc4). if reset is held at vil but not within vss 0.3v, the standby current will be greater. the reset pin may be tied to system reset circuitry. a system reset would that also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset is asserted during a program or erase operation, the ry/by pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tready (during embedded algorithms). the system can thus monitor ry/by to determine whether the reset operation is complete. if reset is asserted when a program or erase operation is completed within a time of tready (not during embedded algorithms). the system can read data trh after the reset pin returns to vih. refer to the ac characteristics tables for reset parameters and to figure 14 for the timing diagram. sector group protect operation the mx29lv640t/b features hardware sector group pro- tection. this feature will disable both program and erase operations for these sector group protected. in this de- vice, a sector group consists of four adjacent sectors which are protected or unprotected at the same time. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe, (sug- gest vid = 12v) a6 = vil and ce = vil. (see table 2) programming of the protection circuitry begins on the falling edge of the we pulse and is terminated on the rising edge. please refer to sector group protect algo- rithm and waveform. mx29lv640t/b also provides another method. which re- quires vid on the reset only. this method can be imple- mented either in-system or via programming equipment. this method uses standard microprocessor bus cycle timing. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih). when a1=1, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will produce 00h for the unprotected sector. in this mode, the addresses, except for a1, are don't care. address locations with a1 = vil are reserved to read manufacturer and device codes. (read silicon id) it is also possible to determine if the group is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector. chip unprotect operation the mx29lv640t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih. (see table 2) refer to chip unprotect algorithm and wave- form for the chip unprotect algorithm. the unprotect mechanism begins on the falling edge of the we pulse and is terminated on the rising edge. mx29lv640t/b also provides another method. which re- quires vid on the reset only. this method can be imple- mented either in-system or via programming equipment. this method uses standard microprocessor bus cycle timing.
18 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b it is also possible to determine if the chip is unprotect in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs (q0-q7) for an unprotect sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. write protect (wp) the write protect function provides a hardware method to protect boot sectors without using v id . if the system asserts vil on the wp pin, the device disables program and erase functions in the two "outer- most" 8 kbyte boot sectors independently of whether those sectors were protected or unprotect using the method described in sector/sector group protection and chip unprotect". the two outermost 8 kbyte boot sec- tors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-config- ured device. if the system asserts vih on the wp pin, the device reverts to whether the two outermost 8k byte boot sec- tors were last set to be protected or unprotect. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotect using the method described in "sector/sector group pro- tection and chip unprotect". note that the wp pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. temporary sector group unprotect operation this feature allows temporary unprotect of previously protected sector to change data in-system. the tempo- rary sector unprotect mode is activated by setting the reset pin to vid(11.5v-12.5v). during this mode, for- merly protected sectors can be programmed or erased as unprotect sector. once vid is remove from the re- set pin, all the previously protected sectors are pro- tected again. silicon id read operation flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. mx29lv640t/b provides hardware method to access the silicon id read operation. which method requires vid on a9 pin, vil on ce, oe, a6, and a1 pins. which apply vil on a0 pin, the device will output mxic's manufac- ture code of c2h. which apply vih on a0 pin, the device will output mx29lv640t/b device code of c9h/cbh. verify sector group protect status operation mx29lv640t/b provides hardware method for sector group protect status verify. which method requires vid on a9 pin, vih on we and a1 pins, vil on ce, oe, a6, and a0 pins, and sector address on a16 to a21 pins. which the identified sector is protected, the device will output 01h. which the identified sector is not protect, the device will output 00h. data protection the mx29lv640t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically re- sets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down tran- sition or system noise.
19 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b secured silicon sector the mx29lv640t/b features a otp memory region where the system may access through a command se- quence to create a permanent part identification as so called electronic serial number (esn) in the device. once this region is programmed, any further modifica- tion on the region is impossible. the secured silicon sector is a 128 words in length, and uses a secured silicon sector indicator bit (q7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevent duplication of a fac- tory locked part. this ensures the security of the esn once the product is shipped to the field. the mx29lv640t/b offers the device with secured sili- con sector either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory , and has the secured silicon sector indicator bit permanently set to a "1". the cus- tomer-lockable version is shipped with the secured sili- con sector unprotected, allowing customers to utilize that sector in any form they prefer. the customer-lock- able version has the secured sector indicator bit perma- nently set to a "0". therefore, the secured silicon sec- tor indicator bit prevents customer, lockable device from being used to replace devices that are factory locked. the system access the secured silicon sector through a command sequence (refer to "enter secured silicon/ exit secured silicon sector command sequence). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the address normally occupied by the last sector sa134 (for mx29lv640t) or first sector sa0 (for MX29LV640B). once entry the secured silicon sec- tor the operation of boot sectors is disabled but the op- eration of main sectors is as normally. this mode of op- eration continues until the system issues the exit se- cured silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending command to sector sa0. low vcc write inhibit when vcc is less than vlko the device does not ac- cept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control pins to prevent unintentional write when vcc is greater than vlko. write pulse "glitch" protection noise pulses of less than 5ns (typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up sequence the mx29lv640t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we=ce=vil and oe=vih during power up, the device does not accept commands on the rising edge of we. the internal state machine is automatically reset to the read mode on power-up. power supply de coupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd.
20 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b factory locked:secured silicon sector programmed and protected at the factory in device with an esn, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. a factory locked device has an 8-word random esn at address 3fff70h-3fff77h (for mx29lv640t) or 000000h-000007h (for MX29LV640B). customer lockable:secured silicon sector not programmed or protected at the factory as an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word secured silicon sector. programming and protecting the secured silicon sector must be used with caution since, once protected, there is no procedure available for unprotected the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using one of the following procedures: write the three-cycle enter secured silicon sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, except that reset may be at either vih or vid. this allows in- system protection of the secured silicon sector without raising any device pin to a high voltage. note that method is only applicable to the secured silicon sector. write the three-cycle enter secured silicon sector region command sequence, and then alternate method of sector protection described in the :sector group protection and unprotect" section. once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array.
21 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b table 2. mx29lv640t/b command definitions first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycles addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 automatic select (note 7) manufacturer id word 4 555 aa 2aa 55 555 90 x00 c2h byte 4 aaa aa 555 55 aaa 90 x00 c2h device id word 4 555 aa 2aa 55 555 90 x01 ddi byte 4 aaa aa 555 55 aaa 90 x02 secured sector fact- word 4 555 aa 2aa 55 555 90 x03 see ory protect (note 9) byte 4 aaa aa 555 55 aaa 90 x06 note 9 sector group protect word 4 555 aa 2aa 55 555 90 (sa)x02 xx00/ verify (note 8) byte 4 aaa aa 555 55 aaa 90 (sa)x04 xx01 enter secured silicon word 3 555 aa 2aa 55 555 88 sector byte 3 aaa aa 555 55 aaa 88 exit secured silicon word 4 555 aa 2aa 55 555 90 xxx 00 sector byte 4 aaa aa 555 55 aaa 90 xxx 00 program word 4 555 aa 2aa 55 555 a0 pa pd byte 4 aaa aa 555 55 aaa a0 pa pd chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 cfi query (note 12) word 1 55 98 byte 1 aa 98 erase suspend (note 10) 1 ba b0 erase resume (note 11) 1 ba 30 software command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 2 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device (when applicable). all addresses are latched on the falling edge of we or ce, whichever happens later. all data are latched on ris- ing edge of we or ce, whichever happens first.
22 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b notes: 1. see table 1 for descriptions of bus operations. 2. all values are in hexadecimal. 3. except when reading array or automatic select data, all bus cycles are write operation. 4. address bits are don't care for unlock and command cycles, except when pa or sa is required. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode when the device is in the automatic select mode or if q5 goes high. 7. the fourth cycle of the automatic select command sequence is a read cycle. 8. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. in the third cycle of the command sequence, address bit a21=0 to verify sectors 0~63, a21=1 to verify sectors 64~134 for top boot device. 9. the data is 88h for factory locked and 08h for not factory locked. 10.the system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 11.the erase resume command is valid only during the erase suspend mode. 12.command is valid when device is ready to read array data or when device is in automatic select mode. legend: x=don't care ra=address of the memory location to be read. rd=data read from location ra during read operation. pa=address of the memory location to be programmed. addresses are latched on the falling edge of the we or ce pulse, whichever happen later. ddi=data of device identifier c2h for manufacture code c9/cbh (top/bottom) for device code pd=data to be programmed at location pa. data is latched on the rising edge of we or ce pulse. sa=address of the sector to be erase or verified (in autoselect mode). address bits a21-a12 uniquely select any sector.
23 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the automatic select mode. see the "reset command" section, next. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an silicon id read command sequence. once in the silicon id read mode, the reset command must be written to return to reading array data (also applies to silicon id read during erase suspend). if q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). silicon id read command sequence the silicon id read command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 2 shows the address and data requirements. this method is an alternative to that shown in table 1, which is intended for prom programmers and requires v id on address bit a9. the silicon id read command sequence is initiated by writing two unlock cycles, followed by the silicon id read command. the device then enters the silicon id read mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to table for valid sector addresses. the system must write the reset command to exit the automatic select mode and return to reading array data. byte/word program command sequence the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 1 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6, or ry/ by. see "write operation status" for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte/word program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across
24 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b automatic chip/sector erase com- mand the device does not require the system to preprogram prior to erase. the automatic erase algorithm automati- cally pre-program and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 2 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the automatic erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using q7, q6, q2, or ry/by. see "write op- eration status" for information on these status bits. when the automatic erase algorithm is complete, the device pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code for mx29lv640t vih vil 1 1 0 0 1 0 0 1 22c9h (word) xxc9h (byte) device code for MX29LV640B vih vil 1 1 0 0 1 0 1 1 22cbh (word) xxcbh (byte) table 3. silicon id code setup automatic chip/sector erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h, or the sector erase command 30h. returns to reading array data and addresses are no longer latched. figure 3 illustrates the algorithm for the erase operation. see the erase/program operations tables in "ac char- acteristics" for parameters, and to figure 16 for timing diagrams. sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may halt the operation and set q5 to "1" , or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". the mx29lv640t/b contains a silicon-id-read opera- tion to supplement traditional prom programming meth- odology. the operation is initiated by writing the read silicon id command sequence into the command regis- ter. following the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of 22c9h/22cbh for mx29lv640t/b.
25 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the automatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command 80h. two more "unlock" write cycles are then followed by the sector erase command 30h. the sector address is latched on the falling edge of we or ce, whichever happens later , while the command (data) is latched on the rising edge of we or ce, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we or ce, whichever happens later. each successive sector load cycle started by the falling edge of we or ce, whichever happens later must begin within 50us from the rising edge of the preceding we or ce, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode. erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- query command and common flash interface (cfi) mode mx29lv640t/b is capable of operating in the cfi mode. this mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. two commands are required in cfi mode. query command of cfi mode is placed first, then the reset command exits cfi mode. these are described in table 3. the single cycle query command is valid only when the device is in the read mode, including erase suspend, standby mode, and read id mode; however, it is ignored otherwise. the reset command exits from the cfi mode to the read mode, or erase suspend mode, or read id mode. the command is valid only when the device is in the cfi mode. mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after this command has been executed, the command register will initiate erase suspend mode. the state machine will return to read mode automatically after suspend is ready. at this time, state machine only allows the command register to re- spond to the erase resume, program data to, or read data from any sector not selected for erasure. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended blocks. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing.
26 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b table 4-1. cfi mode: identification data values (all values in these tables are in hexadecimal) description address h address h data h (x16) (x8) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code (none) 17 2e 0000 18 30 0000 address for secondary algorithm extended query table (none) 19 32 0000 1a 34 0000 table 4-2. cfi mode: system interface data values description address h address h data h (x16) (x8) vcc supply, minimum (2.7v) 1b 36 0027 vcc supply, maximum (3.6v) 1c 38 0036 vpp supply, minimum (none) 1d 3a 0000 vpp supply, maximum (none) 1e 3c 0000 typical timeout for single word/byte write (2 n us) 1f 3e 0004 typical timeout for maximum size buffer write (2 n us) 20 40 0000 typical timeout for individual block erase (2 n ms) 21 42 000a typical timeout for full chip erase (2 n ms) 22 44 0000 maximum timeout for single word/byte write times (2 n x typ) 23 46 0005 maximum timeout for maximum size buffer write times (2 n x typ) 24 48 0000 maximum timeout for individual block erase times (2 n x typ) 25 4a 0004 maximum timeout for full chip erase times (not supported) 26 4c 0000 table 4-3. cfi mode: device geometry data values description address h address h data h (x16) (x8) device size (2 n bytes) 27 4e 0017 flash device interface code (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in multi-byte write (not supported) 2a 54 0000 2b 56 0000
27 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b table 4-4. cfi mode: primary vendor-specific extended query data values description address h address h data h (x16) (x8) query-unique ascii string "pri" 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0031 address sensitive unlock (0=required, 1= not required) 45 8a 0000 erase suspend (2= to read and write) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0004 temporary sector unprotect (1=supported) 48 90 0001 sector protect/unprotect scheme 49 92 0004 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode type (0=not supported) 4b 96 0000 page mode type (0=not supported) 4c 98 0000 acc (acceleration) supply minimum 4dh 9a 00h 00h=not supported, d7-d4: volt, d3-d0:100mv acc (acceleration) supply maximum 4eh 9c 00h 00h=not supported, d7-d4: volt, d3-d0:100mv top/bottom boot sector flag 4fh 9e 0002h/ 02h=bottom boot device, 03h=top boot device 0003h number of erase block regions 2c 58 0002 erase block region 1 information 2d 5a 0007 [2e,2d] = # of blocks in region -1 2e 5c 0000 [30, 2f] = size in multiples of 256-bytes 2f 5e 0020 30 60 0000 31h 62 007eh erase block region 2 information (refer to cfi publication 100) 32h 64 0000h 33h 66 0000h 34h 68 0001h 35h 6a 0000h erase block region 3 information (refer to cfi publication 100) 36h 6c 0000h 37h 6e 0000h 38h 70 0000h 39h 72 0000h erase block region 4 information (refer to cfi publication 100) 3ah 74 0000h 3bh 76 0000h 3ch 78 0000h
28 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b table 5. write operation status notes: 1. performing successive read operations from the erase-suspended sector will cause q2 to toggle. 2. performing successive read operations from any address will cause q6 to toggle. 3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the q2 bit. however, successive reads from the erase-suspended sector will cause q2 to toggle. write operation status the device provides several bits to determine the status of a write operation: q2, q3, q5, q6, q7, and ry/by. table 10 and the following subsections describe the func- tions of these bits. q7, ry/by, and q6 each offer a method for determining whether a program or erase op- eration is complete or in progress. these three bits are discussed first. status q7 q6 q5 q3 q2 ry/by note1 note2 byte/word program in auto program algorithm q7 toggle 0 n/a no 0 toggle auto erase algorithm 0 toggle 0 1 toggle 0 erase suspend read 1 no 0 n/a toggle 1 (erase suspended sector) toggle in progress erase suspended mode erase suspend read data data data data data 1 (non-erase suspended sector) erase suspend program q7 toggle 0 n/a n/a 0 byte/word program in auto program algorithm q7 toggle 1 n/a no 0 toggle exceeded time limits auto erase algorithm 0 toggle 1 1 toggle 0 erase suspend program q7 toggle 1 n/a n/a 0
29 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b q7: data polling the data polling bit, q7, indicates to the host system whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing erase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. if a pro- gram address falls within a protected sector, data poll- ing on q7 is active for approximately 1 us, then the de- vice returns to reading array data. during the automatic erase algorithm, data polling pro- duces a "0" on q7. when the automatic erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on q7. this is analo- gous to the complement/true datum output described for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement, or "0". the system must provide an address within any of the sectors se- lected for erasure to read valid status information on q7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data polling on q7 is active for approximately 100 us, then the device returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchronously with q0-q6 while output enable (oe) is asserted low. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we or ce, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to con- trol the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles for 100us and returns to reading array data. if not all se- lected sectors are protected, the automatic erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the auto- matic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to de- termine which sectors are erasing or erase-suspended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 4 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we or ce, whichever happens first pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read
30 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 4 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. q5:program/erase timing q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data polling and toggle bit are the only operating functions of the device under this condi- tion. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte/word pro- gramming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be re- used). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. the q5 failure condition may appear if the system tries to program a to a "1" location that is previously pro- grammed to "0". only an erase operation can change a "0" back to a "1". under this condition, the device halts the operation, and when the operation has exceeded the timing limits, q5 produces a "1". q3:sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase com- mand sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is
31 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept addi- tional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. if the time between additional erase commands from the system can be less than 50us, the system need not to monitor q3. ry/by:ready/busy output the ry/by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by status is valid after the rising edge of the final we pulse in the command sequence. since ry/by is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to vcc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode.
32 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe, and reset (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on pins a9, oe, and reset is -0.5 v. during voltage transitions, a9, oe, and reset may overshoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc input volt- age on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40 c to +85 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
33 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b notes: 1. on the wp pin only, the maximum input load current when wp = vil is 5.0ua 2. maximum icc specifications are tested with vcc = vcc max. 3. the icc current listed is typically is less than 2 ma/mhz, with oe at vih . typical specifications are for vcc = 3.0v. 4. icc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. not 100% tested. dc characteristics ta=-40 c to 85 c, vcc=2.7v~3.6v para- meter description test conditions min typ max unit i li input load current (note 1) vin = vss to vcc , 1.0 ua vcc = vcc max i lit a9 input leakage current vcc=vcc max; a9 = 12.5v 35 ua i lo output leakage current vout = vss to vcc , 1.0 ua vcc= vcc max icc1 vcc active read current ce= vil, oe = vih 5 mhz 9 16 ma (notes 2,3) 1 mhz 2 4 ma icc2 vcc active write current ce= v il , oe = v ih 26 30 ma (notes 2,4,6) icc3 vcc standby current ce,reset=vcc 0.3v 0.2 15 ua (note 2) wp=vih icc4 vcc reset current reset=vss 0.3v 0.2 15 ua (note 2) wp=vih icc5 automatic sleep mode vil = v ss 0.3 v, 0.2 15 ua (note 2,5) vih = vcc 0.3 v, wp=vih vil input low voltage -0.5 0.8 v vih input high voltage 0.7xvcc vcc+0.3 v vid voltage for autoselect and vcc = 3.0 v 10% 11.5 12.5 v temporary sector unprotect vol output low voltage iol= 4.0ma,vcc=vcc min 0.45 v voh1 output high voltage ioh=-2.0ma,vcc=vcc min 0.85vcc v voh2 ioh=-100ua,vcc=vcc min vcc-0.4 v vlko low vcc lock-out voltage 1.5 v (note 4)
34 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b switching test circuits waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state(high z) key to switching waveforms switching test waveforms test specifications test condition 90 120 unit output load 1 ttl gate output load capacitance, cl 30 100 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm 3.3v 1.5v 1.5v measurement level 3.0v 0.0v output input
35 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b ac characteristics read-only operations ta=-40 c to 85 c, vcc=2.7v~3.6v parameter speed options std. description test setup 90 120 unit trc read cycle time (note 1) min 90 120 ns tacc address to output delay ce, oe=vil max 90 120 ns tce chip enable to output delay oe=vil max 90 120 ns toe output enable to output delay max 35 50 ns tdf chip enable to output high z (note 1) max 30 30 ns tdf output enable to output high z (note 1) max 30 30 ns toh output hold time from address, ce or oe, min 0 ns whichever occurs first read min 0 ns toeh o utput enable hold time t oggle and min 10 ns (note 1) data polling notes: 1. not 100% tested. 2. see switching test circuits and test specifications table for test specifications.
36 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 1. command write operation addresses ce oe we din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid read/reset operation fig 2. read timing waveforms addresses ce oe tacc we vih vil vih vil vih vil vih vil 0v vih vil voh vol high z high z data valid toe toeh tdf tce trh trh trc outputs reset ry/by toh add valid
37 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 3. reset timing waveform ac characteristics parameter description test setup all speed options unit tready1 reset pin low (during automatic algorithms) max 20 us to read or write (see note) tready2 reset pin low (not dur ing automatic max 500 ns algorithms) to read or write (see note) trp reset pulse width (not during automatic algorithms) min 500 ns trh reset high time before read(see note) min 50 ns trb ry/by recovery time(to ce, oe go low) min 0 ns trpd reset low to standby mode min 20 us note:not 100% tested trh trb tready1 trp trp tready2 ry/by ce, oe reset reset timing not during automatic algorithms reset timing during automatic algorithms ry/by ce, oe reset
38 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b erase/program operation fig 4. automatic chip/sector erase timing waveform twc address oe ce 55h 2aah sa 30h in progress complete va va notes: 1.sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah 555h for chip erase tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph 10 for chip erase tvcs we data ry/by vcc
39 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes write data 10h address 555h write data 55h address 2aah data = ffh ? yes auto erase completed data poll from system no
40 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 6. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah auto sector erase completed data poll from system yes no data=ffh? last sector to erase ? no yes
41 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 7. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
42 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 8. secured silicon sector protected algorithms flowchart start enter secured silicon sector data = 01h ? no ye s wait 1us first wait cycle data=60h second wait cycle data=60h a6=0, a1=1, a0=0 wait 300us write reset command device failed secured sector protect complete
43 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b ac characteristics erase and program operations ta=-40 c to 85 c, vcc=2.7v~3.6v parameter speed options std. description 90 120 unit twc write cycle time (note 1) min 90 120 ns tas address setup time min 0 ns taso address setup time to oe low during toggle bit polling min 15 ns tah address hold time min 45 50 ns taht address hold time f rom ce or oe high during toggle min 0 ns bit polling tds data setup time min 45 50 ns tdh data hold time min 0 ns toeph output enable high during toggle bit polling min 20 ns tghwl read recovery time before write min 0 ns (oe high to we low) tghel read recovery time before write min 0 ns tcs ce setup time min 0 ns tch ce hold time min 0 ns twp write pulse width min 35 50 ns twph wr ite pulse width high min 30 ns twhwh1 programming operation byte typ 9 us word typ 11 us twhwh2 sector erase operation (note 2) typ 1.6 sec tvcs vcc setup time (note 1) min 50 us trb write recovery time from ry/by min 0 ns tbusy program/erase valid to ry/by delay min 90 ns notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
44 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 9. automatic program timing waveforms twc address oe ce a0h xxxh pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tbusy trb tcs twph tvcs we data ry/by vcc
45 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b ac characteristics alternate ce controlled erase and program operations parameter speed options std. description 90 120 unit twc write cycle time (note 1) min 90 120 ns tas address setup time min 0 ns tah address hold time min 45 50 ns tds data setup time min 45 50 ns tdh data hold time min 0 ns tghel read recovery time before write min 0 ns (oe high to we low) tws we setup time min 0 ns twh we hold time min 0 ns tcp ce pulse width min 45 50 ns tcph ce pulse width high min 30 ns twhwh1 programming operation byte typ 9 us word typ 11 us twhwh2 sector erase operation (note 2) typ 1.6 sec notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
46 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 10. ce controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we oe ce data q7 pa data polling dout reset ry/by notes: 1.pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2.figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
47 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 11. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify word ok ? yes auto program completed data poll from system increment address last address ? no no
48 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b sector group protect/chip unprotect fig 12. sector group protect / chip unprotect waveform (reset control) note: for sector group protect a6=0, a1=1, a0=0. for chip unprotect a6=1, a1=1, a0=0 sector group protect:150us chip unprotect:15ms 1us vid vih data sa, a6 a1, a0 ce we oe valid* valid* status valid* sector group protect or chip unprotect 40h 60h 60h verify reset
49 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 13. in-system sector group protect/chip unprotect algorithms with reset=vid start plscnt=1 reset=vid wait 1us set up sector address sector protect: write 60h to sector address with a6=0, a1=1, a0=0 wait 150us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 reset plscnt=1 remove vid from reset write reset command sector protect algorithm chip unprotect algorithm sector protect complete remove vid from reset write reset command sector unprotect complete device failed temporary sector unprotect mode increment plscnt increment plscnt first write cycle=60h? set up first sector address protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect: write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=01h? plscnt=25? device failed start plscnt=1 reset=vid wait 1us first write cycle=60h? all sectors protected? data=00h? plscnt=1000? last sector verified? ye s ye s ye s no no no ye s ye s ye s ye s ye s ye s no no no no no no protect another sector? reset plscnt=1 temporary sector unprotect mode
50 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 14. sector group protect timing waveform (a9, oe control) toe data oe we 12v 3v 12v 3v ce a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h a21-a16 sector address parameter description test setup all speed options unit tvlht v oltage transition time min. 4 us twpp1 write pulse width for sector group protect min. 100 ns toesp oe setup time to we active min. 4 us ac characteristics
51 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 15. sector group protection algorithm (a9, oe control) start set up sector addr plscnt=1 sector protection complete data=01h? ye s . oe=vid,a9=vid,ce=vil a6=vil activate we pulse time out 150us set we=vih, ce=oe=vil a9 should remain vid read from sector addr=sa, a1=1 protect another sector? remove vid from a9 write reset command device failed plscnt=32? ye s no no
52 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 16. chip unprotect timing waveform (a9, oe control) toe data oe we 12v 3v 12v 3v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 f0h
53 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 17. chip unprotect flowchart (a9, oe control) start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe=a9=vid ce=vil,a6=1 activate we pulse time out 15ms set oe=ce=vil a9=vid,a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
54 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 18. temporary sector group unprotect waveforms ac characteristics parameter description test all speed options unit setup tvidr vid rise and f all time (see note) min 500 ns trsp reset setup time for temporary sector unprotect min 4 us trrb reset hold time from ry/by high for temporary min 4 us sector group unprotect reset ce we ry/by tvidr 12v 0 or 3v vil or vih trsp tvidr program or erase command sequence trrb
55 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 19. temporary sector group unprotect flowchart start reset = vid (note 1) perform erase or program operation reset = vih temporary sector unprotect completed(note 2) operation completed 2. all previously protected sectors are protected again. note : 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v
56 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 20. silicon id read timing waveform tacc tce tacc toe toh toh tdf data out 00c2h 22c9h for top 22cbh for bottom vid vih vil add a9 add ce a1 oe we add a0 data out data q0-q15 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
57 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b write operation status fig 21. data polling timing waveforms (during automatic algorithms) notes: va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle . tdf tce tch toe toeh tacc trc toh address ce oe we q7 q0-q6 ry/by tbusy status data status data status data complement true valid data va va va high z high z valid data tr u e
58 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 22. data polling algorithm notes: 1.va=valid address for programming. 2.q7 should be rechecked even q5="1" because q7 may change simultaneously with q5. read q7~q0 add.=va(1) read q7~q0 add.=va start q7 = data ? q5 = 1 ? q7 = data ? fail pass no no (2) no ye s ye s ye s
59 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 23. toggle bit timing waveforms (during automatic algorithms) notes: va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tch toe toeh tacc trc toh address ce oe we q6/q2 ry/by tdh valid status valid status (first read) valid status (second read) (stops toggling) valid data va va va va valid data
60 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6= toggle? program/erase operation not complete, write reset command yes program/erase operation complete fig 24. toggle bit algorithm note: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1".
61 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b fig 25. q6 versus q2 notes: the system can use oe or ce to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase suspend read erase erase resume erase complete erase q6 q2
62 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. limits parameter min. typ.(2) max. units sector erase time 0.9 15 sec chip erase time 45 65 sec byte programming time 9 300 us word programming time 11 360 us chip programming time byte mode 50 160 sec word mode 45 140 sec erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance (1) note: 1. not 100% tested, excludes external system level over head. 2. typical program and erase times assume the following condition= 25 c,3.0v vcc. additionally, programming typicals assume checkerboard pattern. parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz parameter test conditions min unit minimum pattern data retention time 150 10 years 125 20 years data retention
63 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b ordering information plastic package part no. access time ball pitch/ package remark (ns) ball size mx29lv640ttc-90 90 48 pin tsop (normal type) mx29lv640ttc-12 120 48 pin tsop (normal type) MX29LV640Btc-90 90 48 pin tsop (normal type) MX29LV640Btc-12 120 48 pin tsop (normal type) mx29lv640tti-90 90 48 pin tsop (normal type) mx29lv640tti-12 120 48 pin tsop (normal type) MX29LV640Bti-90 90 48 pin tsop (normal type) MX29LV640Bti-12 120 48 pin tsop (normal type) mx29lv640txbc-90 90 0.8mm/0.3mm 63 ball csp mx29lv640txbc-12 120 0.8mm/0.3mm 63 ball csp MX29LV640Bxbc-90 90 0.8mm/0.3mm 63 ball csp MX29LV640Bxbc-12 120 0.8mm/0.3mm 63 ball csp mx29lv640txbi-90 90 0.8mm/0.3mm 63 ball csp mx29lv640txbi-12 120 0.8mm/0.3mm 63 ball csp MX29LV640Bxbi-90 90 0.8mm/0.3mm 63 ball csp MX29LV640Bxbi-12 120 0.8mm/0.3mm 63 ball csp mx29lv640txec-90 90 0.8mm/0.4mm 63 ball csp mx29lv640txec-12 120 0.8mm/0.4mm 63 ball csp MX29LV640Bxec-90 90 0.8mm/0.4mm 63 ball csp MX29LV640Bxec-12 120 0.8mm/0.4mm 63 ball csp mx29lv640txei-90 90 0.8mm/0.4mm 63 ball csp mx29lv640txei-12 120 0.8mm/0.4mm 63 ball csp MX29LV640Bxei-90 90 0.8mm/0.4mm 63 ball csp MX29LV640Bxei-12 120 0.8mm/0.4mm 63 ball csp mx29lv640txcc-90 90 1mm/0.4mm 64 ball csp mx29lv640txcc-12 120 1mm/0.4mm 64 ball csp MX29LV640Bxcc-90 90 1mm/0.4mm 64 ball csp MX29LV640Bxcc-12 120 1mm/0.4mm 64 ball csp mx29lv640txci-90 90 1mm/0.4mm 64 ball csp mx29lv640txci-12 120 1mm/0.4mm 64 ball csp MX29LV640Bxci-90 90 1mm/0.4mm 64 ball csp MX29LV640Bxci-12 120 1mm/0.4mm 64 ball csp
64 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b part no. access time ball pitch/ package remark (ns) ball size mx29lv640ttc-90g 90 48 pin tsop pb-free (normal type) mx29lv640ttc-12g 120 48 pin tsop pb-free (normal type) MX29LV640Btc-90g 90 48 pin tsop pb-free (normal type) MX29LV640Btc-12g 120 48 pin tsop pb-free (normal type) mx29lv640tti-90g 90 48 pin tsop pb-free (normal type) mx29lv640tti-12g 120 48 pin tsop pb-free (normal type) MX29LV640Bti-90g 90 48 pin tsop pb-free (normal type) MX29LV640Bti-12g 120 48 pin tsop pb-free (normal type)
65 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b package information
66 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b
67 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b
68 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b
69 p/n:pm0920 rev. 1.2, nov. 05, 2003 mx29lv640t/b revision history revision no. description page date 1.0 1. to modified the max. icc current from 5ua to 15ua p33 jul/22/2003 2. to added 63csp with 0.4mm ball size package information p63,66 1.1 1. to corrected cfi code in table 4-3 device geometry data values p27 oct/28/2003 2. to added pb-free part no. for 48-tsop package p64 1.2 1. removed "preliminary" from title p1 nov/05/2003
mx29lv640t/b m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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